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ABOUT NEUROPHOS The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. Join us and shape the future of computing! Position Overview: We are seeking a talented ML Compiler Engineer to join our engineering team and lead the development of our compiler. This role focuses on compiler development for our novel LLM accelerator architecture. This is one of several software stacks that seamlessly bridge high-level AI workloads with our custom hybrid optical-electronic compute hardware, enabling customers to realize game-changing performance. Location: San Jose, CA or Austin, TX. Full-time onsite position. Key Responsibilities: - Design and implement toolchains for our custom LLM accelerator architecture - Develop optimization strategies that bridge software algorithms to hardware implementations - Design and implement custom compiler components, including IR dialects, graph transformations, and lowering passes - Optimize computational graphs and memory access patterns for our hardware architecture - Integrate with existing ML frameworks (e.g., PyTorch, JAX, Triton). - Build and maintain test infrastructure to ensure compiler correctness and performance Qualifications: - Master's degree in Computer Science or related field - 5+ years of experience in compiler development - Expert-level proficiency in Python and C - Experience with hardware compilers - Familiarity with Large Language Model architectures and their computational requirements - Hands-on experience with compiler frameworks and code optimization techniques - Deep understanding of computer architecture, memory hierarchies, and parallel computing concepts - Experience with AI/ML accelerators (GPUs, TPUs, FPGAs) and their programming models Preferred Skills: - PhD in Computer Science or related field - 7+ years of industry experience - Strong background in graph theory and graph transformations in a compiler or optimization context; MLIR experience is a plus - Experience writing programs that parse, analyze, and mutate programs as abstract syntax trees - Experience in instrumenting and debugging parallel programs - Experience with structured, human-supervised AI/agentic coding workflows - Experience with LLM quantization techniques and model optimization - Experience with high-performance computing and low-latency system design - Familiarity with deep learning frameworks and neural network optimization Technical Skills - Programming Languages: Python and C (essential), Assembly - Compiler Frameworks: LLVM, MLIR, GCC, custom backend development - Graph Theory: Graph algorithms, graph rewriting systems, DAG optimization - AST Processing: Parsing, analysis, and transformation of abstract syntax trees - Testing & QA: pytest, GoogleTest, or similar framewo