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Huawei envisions a world where technology connects people, empowers industries, and unlocks human potential. Guided by its mission to enrich lives through communication and intelligent innovation, Huawei stands at the forefront of global digital transformation. As a leader in Information and Communications Technology (ICT), the company pioneers breakthroughs in artificial intelligence, cloud computing, and smart devices—building the intelligent foundation of a fully connected world. Through its Carrier, Enterprise, and Consumer business groups, Huawei delivers resilient digital infrastructure, advanced cloud and AI platforms, and transformative devices that enable progress at every level. Supporting 45 of the world’s top 50 telecom operators and serving one-third of the global population across more than 170 countries, Huawei is shaping a future where connectivity becomes a powerful catalyst for opportunity and sustainable growth. Huawei Heisenberg Research Center (Munich)  is responsible for advanced technology research, architectural development, design and strategic engineering of our products. The Applied Network Technology Lab (ANTL) plays a leading role in researching new networking technologies and delivering novel next generation networking solutions. Our research areas include but not limited to Internet and networking protocols, Deterministic Networking, Time-Sensitive Networking, and Industrial Ethernet. Join us as a Intern - Next-generation Computer Architecture for Racks and SuperPods (m/f/d) Your mission Designing next-generation rack and SuperPod architectures that combine elasticity through resource pooling with optimal performance enabled by holistic co-design across applications, parallel programming models, interconnect fabrics, and compute, memory, and switch chip architectures. On the communication side , the work architects scalable, high-bandwidth, and low-latency scale-up fabrics across multiple chips at rack and SuperPod scale. On the memory side , it explores richer protocol semantics beyond traditional load/store operations to reduce unnecessary data movement and rethinks memory hierarchies to expose large-scale capacity with near-local latency. On the compute side , it analyzes the requirements of General Compute and Generative AI workloads and their parallel programming models to fully leverage large-scale system resources. Investigate and prototype new architectural features, including but not limited to: o Tiered Memory: Explore advanced memory organizations, including hardware-managed caching, to enable software-transparent, fine-grained promotion and demotion of cache lines across the memory hierarchy. o Prefetching/Speculation: Evaluate and design existing and next-generation hardware prefetching and speculation mechanisms to effectively hide local and remote memory latencies at rack and SuperPod scale. o Near-Memory/Network Processing: Develop support for key primitives executed at the memory and network layers to minimize unnecessary data movement across sparse, dense, and pointer-based data structures. o Workload-Centric Co-Design: Study optimal parallelization strategies at rack and SuperPod scale for both General Compute and Generative AI workloads, and design dedicated hardware support for widely used parallel programming primitives such as RPCs and collective communication. Write reports and papers on the research results and present them. Your areas of expertise Enrolled MSc student in Computer Science, Electrical Engineering, or related field Background in Computer Architecture and Computer Fabrics is a must Creativity and the ability to think outside the box to develop innovative technologies Research experience in at least one of the following areas: o Computer Architecture: Modern cache hierarchies, cache coherence protocols, memory systems, hardware prefetchers, and the memory-s