Job Opportunities API

At  Kandou , we are redefining the economics of AI infrastructure. Our mission is to  democratise AI by significantly reducing the Total Cost of Ownership (TCO)  of hardware systems — a critical barrier to scalable adoption. Our proprietary  MIMO-over-copper technology  powers a  high-performance, chiplet-based AI memory fabric  that is both  scalable and energy-efficient . Unlike traditional interconnects, our solution  reduces power consumption significantly  while preserving  high bandwidth and ultra-low latency  — unlocking unprecedented efficiency for AI training and inference at scale. Kandou’s architecture is not just an incremental improvement — it’s a  foundational shift  in how AI hardware is built for the future. We are actively seeking for a Digital Design Engineer Location: L ausanne (St-Sulpice), Switzerland Responsibility • Concept definition, analog to digital interface specification • RTL design with basics of Dft and IP verification • Logic synthesis, Timing analysis – desired • Close interaction with Verification engineers, Analog/Mixed signal designers • Develop block level specifications of very high-speed digital circuits that meet key performance targets based on system level requirement • Design and verification of very high-speed digital circuits • Support for post-silicon lab bring-up, debug, characterization and productization • Analysis and understanding of high-speed serial protocols (e.g., USB4, PCIe) • Analog/digital interface specification in close cooperation with analog/mixed-signal designers • Validation and bring-up of chips in the lab • Close interaction with verification and physical implementation engineers to verify circuit functionality and compliance with area, timing, and power requirements • Support and interact with customers on requirements, design specifications, performance results and product delivery • Support IP and chip level integration • Manage workload and schedules and report to internal management team and external customers Required Experience • 5-10 years’ experience in digital design of key circuits in multi-Gigabit serial data-link transceivers, DDR and low power high performance modern memory interfaces and experience in the semiconductor industry • Strong technical background in design of high-speed digital circuits in deep-submicron CMOS technologies • Proven experience in complex digital design and verification of data processing systems • Proven experience in design and verification of complex regulation systems (configuration, calibration, and dynamic adaption) • Experience in industry standard design EDA tools for design, simulation, and verification • Experience in digital high-speed blocks, CMOS High Speed interface competence would be a preference • Exposure to the Cadence toolset • Experience with multi-Gigabit serial data transceivers is highly desirable • Experience with analog/digital control interfaces is valuable Required Skills • Strong interest in the design of digital circuits and blocks for multi-Gigabit serial ana parallel data-link transceivers, DDR and low power high performance memory and communication interfaces • Strong scripting and tool setup skill • Strong analytical skills to translate system-level requirements into design • Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player • RTL coding skills, CDC and Linting knowledge • Understanding of verification tools and methodologies is an advantage • Knowledge of synthesis, STA and signal processing techniques is an advantage • Advanced knowledge of high-speed and low-power design techniques and high-speed serial protocols • Scripting (Python preferred) and tool setup skills Required Education • Proven experience and/or Masters or Ph.D. in E.E., Communications or other relevant fields • MSc in electronics/electrical engineering (equivalent or higher) https://kandou.ai/