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Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

Erbity Private Limited
CompanyErbity Private Limited
CategoryUncategorised
LocationHyderabad
RemoteHybrid
EmploymentFull-time
LevelNot stated
SalaryNot stated by the employer
Posted31 Mar 2026
Last verified7 Aug 2026
SourceEmployer ATS (workable)
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Description
If breaking designs before tapeout sounds fun, you’re exactly who this is for. 4–6 years in IP/Block/Subsystem verification Strong expertise in SystemVerilog and UVM methodology Experience building test plans, environments, and testbenches Strong RTL debugging, assertions, and coverage analysis Knowledge of AXI/AHB and protocols like DDR, PCIe, NVMe Experience in end-to-end verification from plan to signoff Exposure to mentoring and working in global teams Strong communication and problem-solving skills If you believe first-pass silicon is discipline, not luck, let’s connect.