Celero Communications, Inc.
Telecommunications · SME · US
17 open rolesFirst seen 2026-07-30
Open roles
| Role | Location | Remote | Level | Salary | Posted |
|---|---|---|---|---|---|
| Sr. Principal Application Engineer | Irvine | On-site | — | — | 31 Jul 2026 |
| Senior/Principal High-Speed Analog Layout Design Engineer | Córdoba | On-site | — | — | 30 Jul 2026 |
| Principal Design Validation & Test (DVT) Engineer | Irvine | On-site | — | — | 30 Jul 2026 |
| Marketing Director Marketing | Irvine | On-site | Director | — | 21 Jul 2026 |
| Senior/Principal Full-Chip Physical Verification Engineer | San Jose | On-site | — | — | 10 Jul 2026 |
| Senior/Principal High-Speed Analog Layout Design Engineer | Irvine | On-site | — | — | 19 Jun 2026 |
| Senior/Principal Physical Design Engineer Engineering | San Jose | On-site | Lead | — | 12 Jun 2026 |
| Senior Technical Recruiter HR & Recruiting | Irvine | On-site | Senior | — | 12 May 2026 |
| ASIC Design Engineer Engineering | Ottawa | On-site | — | — | 24 Apr 2026 |
| Principal Product Engineer Engineering | Irvine | On-site | Lead | — | 14 Apr 2026 |
| Principal PLL Design Engineer | Irvine | On-site | — | — | 6 Apr 2026 |
| Senior DSP Firmware Engineer | Ottawa | On-site | — | — | 23 Mar 2026 |
| DSP - FEC Design Engineer | Ottawa | On-site | — | — | 17 Mar 2026 |
| Optical DSP Design Engineer | Ottawa | On-site | — | — | 17 Mar 2026 |
| Principal Analog Design Engineer Engineering | Irvine | On-site | Lead | — | 27 Feb 2026 |
| Staff ASIC Design Engineer Engineering | San Jose | On-site | — | — | 20 Feb 2026 |
| ASIC Design Verification Engineer Engineering | Ottawa | On-site | — | — | 19 Feb 2026 |