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Cambridge, UK | Full-time | Permanent | Hybrid   Salary: £60,000 to £88,000 (DOE) + Bonus + Benefits     The salary range for this role is broad, as we are able to consider varying levels of experience.  Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements. We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.      About us   Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved.  Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.    Having raised more than $125M in funding to date to accelerate our  cutting-edge  R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality.  We’re  making remarkable progress and growing fast.      About the role We have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.    In this exciting role you'll have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.    What you will do   As a Verification / Senior Verification Engineer at Riverlane, you will:  Proactively work with designers and architects to define verification plans based on design specifications. You will take full ownership of detailed test strategies across block-level and system-level designs.   Develop and implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests to ensure every part of the system performs flawlessly.   Maintain the health and evolution of the design verification environment, tracking of regressions, coverage metrics and bugs to ensure our systems meet the highest standards of quality and reliability.    What we need   Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.   Proven experience of testbench design with verification frameworks like UVM/OVM.   Knowledge of SystemVerilog assertion (SVA).   Exposure to different programming languages, such as C, C++ and Python.   A proactive person who can independently define the scope of work.  A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.  Ability to work effectively with ambiguity and changing requirements.  Experience debugging across RTL, simulation, and hardware    Ev