Job Opportunities API

Company Overview Ambiq  is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values:  Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here.   Help Build the Digital Hardware Behind Ultra-Low-Power Edge Intelligence Ambiq is on a mission to enable intelligence everywhere by delivering some of the world’s most energy-efficient semiconductor solutions. Our ultra-low-power MCUs and SoCs power smart wearables, medical devices, connected sensors, and intelligent edge products where performance matters—but every microwatt counts. We are looking for a Senior Staff SoC RTL Engineer to help architect, design, and deliver the digital hardware inside our next-generation products. This is a hands-on individual contributor role for an experienced RTL engineer who wants meaningful ownership across the full silicon lifecycle—from microarchitecture and RTL development through design closure, tapeout, and silicon bring-up. What You’ll Do Define the microarchitecture of digital SoC modules and subsystems Develop production-quality RTL using Verilog and SystemVerilog Own complex blocks from specification through pre-tapeout signoff Integrate internal and third-party IP into MCU and SoC platforms Work with ARM-based CPU subsystems and AMBA-based interconnects such as AHB, APB, or AXI Partner with verification engineers on test planning, debug, and coverage closure Collaborate with Physical Design teams to resolve timing, power, area, and implementation issues Run, analyze, and resolve LINT, CDC, and RDC violations Support FPGA prototyping, silicon bring-up, and post-silicon debug Contribute to low-power design through clock gating, power management, and efficient data movement Mentor less-experienced engineers and contribute to technical decisions across teams What We’re Looking For Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field 8+ years of hands-on ASIC or SoC RTL design experience Strong Verilog and/or SystemVerilog development skills Demonstrated ownership of complex digital blocks, IPs, or subsystems Experience creating or contributing to architecture and microarchitecture specifications Understanding of front-end ASIC development, including synthesis, timing, LINT, CDC, and RDC Experience working with verification and Physical Design teams through design closure Familiarity with ARM-based SoCs, CPU subsystems, or AMBA protocols such as AHB, APB, or AXI Experience supporting tapeout, silicon bring-up, or post-silicon debug Ability to explain design decisions, tradeoffs, and technical risks clearly Strong problem-solving skills and a willingness to remain hands-on Experience That Would Be Especially Valuable ARM Cortex-M or embedded CPU subsystem integration MCU architecture and peripheral integration AMBA interconnect, memory maps, DMA, interrupt controllers, or bus arbitration Low-power SoC design, including UPF, power gating, cloc