Sr. Design Verification Engineer
Phizenix
| Company | Phizenix |
| Category | Engineering |
| Location | Bengaluru |
| Remote | On-site (inferred) |
| Employment | Not stated |
| Level | Senior |
| Salary | Not stated by the employer |
| Posted | 10 Mar 2026 |
| Last verified | 30 Jul 2026 |
| Source | Employer career page (greenhouse) |
Description
Location:
Hybrid, working onsite at our Bangalore offices 3 days per week.
Minimum:
BS in Electrical Engineering, Computer Science, or a related field with 8+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 7 years of industry experience is preferred.
Experience in IP/SoC verification cycle preferably from concept to tape-out to bring-up.
Good knowledge of verification methodologies such as UVM/OVM, etc.
Hands-on ASIC-SoC design verification tests and debug experience.
Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
Good problem-solving skills and the passion to take on challenges (particularly in AI domain).
Passionate about AI and thriving in a fast-paced and dynamic startup culture.
Preferred:
Part of Successful implementation of multiple verification environments and tape-out efforts.
Experience with C/C++ is good
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