Job Opportunities API

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here Develop and maintain power estimation methodologies for AI accelerator SoCs. Build and calibrate energy models for early architectural exploration, design trade-off analysis, and power target definition. Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems. Analyze AI workloads and application use cases to identify opportunities for dynamic and static power reduction. Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other SoC subsystems. Collaborate with architects and RTL designers to implement power-efficient microarchitecture and RTL improvements. Work with physical design teams to evaluate implementation-related power trade-offs. Define representative workloads and sign-off scenarios to improve power analysis coverage. Develop automation, scripts, dashboards, and heuristics to accelerate power analysis and root-cause investigation. Present power analysis results, optimization proposals, and design recommendations to cross-functional teams. Who You Are BS or MS in Electrical Engineering, Computer Engineering, or related field. 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design. Strong understanding of computer architecture and SoC design. Experience with ASIC low-power design techniques. Experience performing RTL and gate-level power analysis. Strong analytical and debugging skills. Experience with Python, Perl, or similar scripting languages. Ability to work independently in a fast-paced environment. Excellent communication and cross-functional collaboration skills. Bonus Points If You Have RTL development experience using Verilog/SystemVerilog. Experience with one or more of the following: Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design. Experience with synthesis, static timing analysis, place-and-route, and implementation flows. Experience using power analysis tools (or equivalent tools) such as: Experience developing power models, budgeting methodologies, and projection flows. Experience analyzing large power datasets using scripting and data analytics. Experience with power management techniques including: Experience correlating pre-silicon power estimates with silicon measurements is a plus. Experience with AI workload characterization and power-performance analysis is a plus. Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation. Early Career - $120,000 - $275,000 + equity Mid Career - $175,000 - $450,000 + equity Senior Career - $275,000 - $475,000 + equity What We Offer A Stake in our success  A cash/equity mix that fits your needs and option to do early exercise Health & Wellness  Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t) Time To Recharge  4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year Support to Parents