FPGA Design Engineer
INTRACOM DEFENSE
| Company | INTRACOM DEFENSE |
| Category | Engineering |
| Location | Koropi |
| Remote | On-site (inferred) |
| Employment | Full-time |
| Level | Not stated |
| Salary | Not stated by the employer |
| Posted | 19 Jan 2026 |
| Last verified | 30 Jul 2026 |
| Source | Employer career page (workable) |
Description
Join Our Team as an FPGA Design Engineer at Intracom Defense (IDE) About Us Join Intracom Defense (IDE) , Greece's top tech defense company. Our mission? To innovate, create, and deliver cutting-edge technology on a global scale. At IDE, we research, design, develop, and manufacture groundbreaking products, systems, and solutions in sectors such as Tactical Communication and Information systems, Missile Electronics, Surveillance solutions, Hybrid Electric Power systems , Next-gen Unmanned Air and Sea platforms and disruptive technologies (such as Artificial Intelligence, Cyber Security). As a key player in international defense, IDE is a registered NATO supplier and participates in international development and production programs, as well as in industrial cooperation programs for the defense sector. Last but not least, IDE is a trusted and leading company in EU research and development programs, where research and innovation are the key elements for the upcoming technological breakthroughs. In IDE we invest in people and technology! We're not just about defense— we're about shaping the future! 📍 Location: Koropi, [East] Suburbs 💻 Working Model: hybrid 🚀 Growth Opportunities: Access to continuous learning, professional development, and career advancement pathways 📈 Reporting to: Hardware RF & FPGA Design Section Manager of the Products Development Department Why you Should Join Us : We’re on the lookout for an FPGA Design Engineer who’s not just a talented engineer but a detail-oriented individual with the passion for making things happen. If you're ready to take the lead and drive innovation, IDE is where you belong. What You ‘ll Be Doing: System Design involvement starting from the early stages of the project. Hierarchy definition and design partitioning in complex, embedded processing systems targeting SoC or high-end FPGAs. Full design flow starting from RTL development and up to final integration and testing on H/W. Design for Testing and Reusability. IP-based design flow particularly in conformance with the latest Vivado/Vitis System Design suites and guidelines from AMD (Xilinx). Complex debugging and trouble-shooting cases through H/W and S/W boundaries in SoC based designs. Collaboration with Software Embedded, Software DSP and RF/Antenna engineers to design and&
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