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About the job Delart is home to a team of world-class engineers and project leaders dedicated to developing the next generation of advanced networking technologies, consumer devices, and innovative technology solutions. Trusted by some of the world’s leading technology companies, we deliver highly scalable, mission-critical solutions that power both consumer and business applications globally. Since our founding in 2017, we have been at the forefront of designing cutting-edge networking, telecommunications, and consumer products, while driving end-to-end project execution and creating transformative technology applications. Overview Lead the end-to-end electrical engineering (EE) verification for cutting-edge consumer electronic devices including VR headsets and wearables, from prototype bring-up through mass production. This hands-on role drives technically rigorous validation across global teams, taking operational ownership of multi-subsystem EE test activities at CM/ODM facilities and ensuring best-in-class hardware quality through each hardware build milestone. Responsibilities Own the planning, scheduling, and execution of comprehensive EE validation test plans across subsystems (Battery/PMIC/Power, SOC, Connectivity, Sensors), ensuring technical sufficiency and resource allocation from P0 through PVT. Define, manage, and report on validation milestones and gating items per hardware build phases (P0, P1, P2, EVT, DVT, PVT), maintaining alignment with program schedule and quality targets. Oversee signal integrity (SI) and power integrity (PI) validation, including activities such as clock parametric testing, power sequencing validation, PDN (Power Distribution Network) characterization, and baseline power consumption measurements. Develop and specify test requirements for bus/interface parametric validation on protocols including I2C, SPI, UART, MIPI, I2S, and high-speed I/O (HSIO). Lead execution teams at CM/ODM (e.g., Huaqin Nanchang), ensuring accurate measurement techniques, thorough documentation, and robust adherence to established SOPs. Drive EE-level debugging and root cause analysis using Design of Experiments (DOE), collaborating closely with design engineering teams to identify, isolate, and resolve hardware issues. Maintain real-time validation progress trackers, JIRA/issue documentation, and status updates for local and global stakeholders. Act as the primary communication bridge between external partners/CMs sites and US-based engineering, facilitating cross-timezone validation activities and technical reporting. Minimum Qualifications BS in Electrical Engineering from an accredited university. 5+ years of experience in EE validation or verification environments for complex electronic systems. Demonstrated expertise in at least two of: signal integrity, power integrity, battery integration, sensors, system coexistence, or memory performance. Hands-on experience with SI verification for digital protocols (I2C, SPI, MIPI, I2S, UART, or similar). Deep understanding of power management: DC/DC supply topologies, power sequencing, and PDN measurement best practices. Strong electrical engineering fundamentals, including the ability to interpret schematic and layout files, and review/understand lab data. Proficiency with standard lab equipment (oscilloscope, power supplies, e-loads, function generators, thermal test setups, and probing). Proven track record in project management for validation—coordinating test teams and activities across multi-site/global environments. Excellent English verbal and written communication skills. Preferred Qualifications MS in Electrical Engineering from a recognized university. 7+ years of hands-on EE lab or hardware validation experience, especially for high-volume consumer electronics. Prior experience collaborating with cross-functional teams in US/Asia and managing validation workstreams at CM/ODM sites (preferabl