Director Post-Silicon Product Engineering
Astera Labs
| Company | Astera Labs |
| Category | Uncategorised |
| Location | San Jose |
| Remote | On-site (inferred) |
| Employment | Not stated |
| Level | Not stated |
| Salary | Not stated by the employer |
| Posted | 3 Jun 2026 |
| Last verified | 30 Jul 2026 |
| Source | Employer career page (greenhouse) |
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview
Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes.
As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle — from characterization and qualification through production ramp and sustaining — across our portfolio of purpose-built connectivity solutions enabling rack-scale AI.
This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to production with uncompromising quality. You'll partner closely with design, validation, operations, and customers to ensure Astera Labs' products set the industry standard for performance and reliability.
Key Responsibilities
Team Leadership & Organization Building
Build, mentor, and lead a high-performing team of product engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure
Define team strategy, priorities, and execution roadmaps aligned with Astera Labs' aggressive product delivery timelines
Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows
Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities
ATE Test Development & Production Excellence
Drive ATE test program development and optimization for wafer sort and final test solutions on the Advantest 93K platform
Own device ATE test yields, test time reduction, and quality metrics with a detailed, data-driven mindset
Establish consistent BKMs for rolling out new ATE test programs across product families
Lead data analysis efforts using tools such as JMP or Spotfire to calculate limits, identify outliers, and drive continuous improvement
Product Qualification & Manufacturing
Define and execute standards-based qualification programs at both product and package level
Partner with OSATs to support high-volume manufacturing through the complete product lifecycle
Ensure seamless production ramp and sustaining operations, delivering quality parts to Astera Labs' hyperscaler and enterprise customers
Drive system-level debug involving test hardware, test programs, and DUT interactions across digital and analog domains
Cross-Functional Technical Leadership
Provide technical leadership in high-speed signaling including NRZ/PAM4 SerDes protocols (PCIe Gen 3+, Ethernet 25G+), and memory interfaces such as (LP)DDR5/4
Partner with silicon design teams to feed back produc
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