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Raspberry Pi is seeking a Digital IC Implementation engineer to join our expanding ASIC team to help deliver our next-generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second-generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production. As a Digital IC Implementation Engineer, you will be expected to work closely with the design team to understand requirements and close ambitious performance, power, and area goals. You will contribute in all aspects of physical design from RTL to GDS, including timing constraints, UPF, synthesis, design discovery, place & route, CTS, STA, formal verification, ECO methodology, and physical verification. The successful candidate will be: Able to demonstrate a good level of understanding in all aspects of the implementation flow, from synthesis through to silicon sign-off. A specialist in at least one area of the flow. Willing to share knowledge and mentor other members of the team. Able to demonstrate excellent interpersonal and communication skills. Able to work on site in our Cambridge office. Requirements Requirements and skills This role requires a good level of experience and a wide range of skills: Multiple tapeouts on advanced technology nodes. Strong understanding of the details of modern place and route flows, and insight into methodologies. Experience of full sign-off for tapeout, including Physical Verification, STA, and Power Integrity. Experience of chip-level floorplanning, hierarchical methodologies, and power grid design. Experience of developing constraints, UPF, and high-quality floorplans. Experience with Synthesis and giving input into RTL designs for better physical QOR. Scripting skills both to drive tools and to analyse results. The following would also be useful: Experience of Cadence implementation tool flow. Experience of implementation complex designs. Advanced FinFET technologies. Good understanding of design/front-end processes. The role is based in Cambridge with an expectation of full-time office attendance. Benefits Competitive salary based on level of experience Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme Life assurance of 4 × base salary Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long-term illness or absence from work Private medical insurance (medical history disregarded) Access to our electric vehicle salary sacrifice scheme, subject to eligibility