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Design Verification Engineer (Silicon Engineering)

SpaceX
CompanySpaceX
CategoryEngineering
LocationPalo Alto
RemoteOn-site (inferred)
EmploymentNot stated
LevelNot stated
SalaryNot stated by the employer
Posted14 Jul 2026
Last verified2 Aug 2026
SourceEmployer career page (greenhouse)
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Description
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)   At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.  We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.    RESPONSIBILITIES:    Responsible for digital ASIC verification at block and system level Write and review test plans, develop test harnesses and test sequences Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks  Responsible for test plan execution, running regressions, code and functional coverage closure Automate test case generation by using Python and MATLAB programs  Contribute towards pre-silicon verification, chip bring-up and post-silicon validation Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs BASIC QUALIFICATIONS: Bachelor’s degree in electrical engineering, computer science or computer engineering 1+ years of experience with design verification and test bench development PREFERRED SKILLS AND EXPERIENCE: Advanced degree in electrical engineering or computer engineering Experience with verification methodologies such as UVM Strong object-oriented programming knowledge Strong problem-solving and coding skills Experience in constrained random verification Expertise in developing test plans, implementing coverage models, and analyzing results Experience with scripting languages, e.g. Python for automation RTL design, chip bring-up, and post-silicon validation experience Ability to work in a dynamic environment with changing needs and requirements ADDITIONAL REQUIREMENTS: Ability to work extended hours and weekends as needed to meet critical milestones COMPENSATION AND BENEFITS:          Pay range:     Design Verification Engineer/Level I: $135,000.00 - $155,000.00/per year     Design Verification Engineer/Level II: $155,000.00 - $210,000.00/per year     Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the abilit
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