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This role is for one of the Weekday's clients Salary range: Rs 2500000 - Rs 7000000 (ie INR 25-70 LPA) Experience: 5+ yrs Location: Bengaluru Job Type: Full-Time We are looking for a highly skilled  Design Verification Engineer  to join our VLSI verification team and contribute to the functional verification of complex SoC and subsystem designs. This role is ideal for professionals with strong expertise in  SoC Verification, SystemVerilog, UVM, and PCIe , who are passionate about delivering high-quality silicon through robust verification methodologies and comprehensive coverage closure. As a Design Verification Engineer, you will work closely with RTL designers, architecture teams, and validation engineers to develop scalable verification environments, execute verification plans, debug complex functional issues, and ensure first-pass silicon success. You will be involved throughout the verification lifecycle, from specification review and testbench development to regression execution, coverage analysis, and verification sign-off. This role offers the opportunity to work on cutting-edge semiconductor products while leveraging industry-leading verification methodologies and protocols. Requirements Key Responsibilities Develop and execute comprehensive verification plans for complex SoC and subsystem designs based on functional specifications. Design, build, and maintain reusable  UVM-based verification environments  using  SystemVerilog . Develop constrained-random test cases, sequences, scoreboards, monitors, assertions, and coverage models to achieve comprehensive functional verification. Verify high-speed interface protocols with a strong focus on  PCIe , while supporting additional protocols such as  DDR ,  Ethernet , and other industry-standard interfaces where applicable. Perform SoC-level integration verification, subsystem verification, and IP-level verification activities. Execute functional and regression testing, analyze failures, perform root cause analysis, and resolve verification issues efficiently. Drive functional coverage, code coverage, assertion coverage, and coverage closure to achieve verification sign-off targets. Collaborate with RTL, architecture, physical design, and validation teams to resolve design issues and improve product quality. Develop and enhance reusable verification components and methodologies to improve verification productivity across projects. Participate in verification reviews, design reviews, and technical discussions to ensure verification completeness and quality. Support post-silicon validation teams by reproducing and debugging functional issues when required. What Makes You a Great Fit Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline. 5+ years of experience in  SoC Design Verification  within semiconductor or ASIC/SoC development environments. Strong hands-on expertise in  SystemVerilog  and  UVM  verification methodology. Proven experience in  SoC Verification , subsystem verification, and reusable UVM testbench development. Strong experience verifying high-speed protocols, particularly  PCIe . Good understanding of additional industry-standard protocols such as  DDR ,  Ethernet , AMBA (AXI/AHB/APB), or similar interfaces. Experience with constrained-random verification, assertions (SVA), functional coverage, code coverage, and regression management. Proficiency using industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa. Strong debugging, analytical, and problem-solving skills with the ability to identify and resolve complex verification challenges. Familiarity with scripting languages such as Python, Perl, or Shell is an advantage. Excellent communication and collaboration skills with the ability to work effectively across cross-functio