Job Opportunities API

If you like connecting design intent with silicon reality, this role hits that sweet spot. 5–9 years in ASIC design and implementation Strong experience in Synthesis, STA, DFT, Lint, and CDC Hands-on with timing constraints and closure Experience with Tempus and PrimeTime tools Strong understanding of MMMC, SDF, and GLS support Experience in timing model generation and validation Ability to collaborate with design and SoC teams Strong analytical and debugging skills If you enjoy solving timing puzzles others avoid, you’ll thrive here.